We're about to start a project and we need to be able to parse RTL files. We want to use ruby, but to save effort we're looking for a pre-built open-source parser for RTL grammar. If not we'll have to write our own (no big problem - it'd be an interesting learning experience at least!).
So first, are there any tools we should be looking at to help us out? (we're looking at coco-ruby and parsetree at the moment)
Second, if there are no tools currently available and we can build a Ruby RTL parser would anyone be interested in us releasing it? (I only work here, I'm not sure if the company would allow us to, but if it's possible would people be interested?)
I'd be interested. I'm in the IC design industry. I wrote a
verilog-2005 parser using antlr/java about a year ago (never
released it). Now I'm into ruby and writing a general parser
that has a superset of the features in antlr. Here is my first
cut at it:
Now that my cursor package (using this for both my character
and token streams) is to a good point, I'm back to working on
my grammar package (renamed because of another rubyforge
"syntax" project).
I wouldn't mind making a verilog parser the first target of
this.
···
--- Kev Jackson <kevin.jackson@it.fts-vn.com> wrote:
Hi all,
We're about to start a project and we need to be able to
parse RTL
files. We want to use ruby, but to save effort we're looking
for a
pre-built open-source parser for RTL grammar. If not we'll
have to
write our own (no big problem - it'd be an interesting
learning
experience at least!).
So first, are there any tools we should be looking at to help
us out?
(we're looking at coco-ruby and parsetree at the moment)
Second, if there are no tools currently available and we can
build a
Ruby RTL parser would anyone be interested in us releasing
it? (I only
work here, I'm not sure if the company would allow us to, but
if it's
possible would people be interested?)
Kev
____________________________________________________
Start your day with Yahoo! - make it your home page http://www.yahoo.com/r/hs
* Phil Tomson <ptkwt@aracnet.com> [2005-08-02 03:51:04 +0900]:
Definitely. Though, I'm more of a VHDL person, I would like to see some
sort of 'Ruby for EDA' website sometime in the future.
I have considered putting one of those together, but am
not sure of the payoff. Most sites like that are full of
dead links and are extremely inactive.
I can host the site if someone can suggest a good infrastructure.
Maybe a Typo frontend and we just require that all the code
has a rubyforge project and can be obtained thru a gem.
In article <20050801125951.14936.qmail@web41103.mail.yahoo.com>,
I'd be interested. I'm in the IC design industry. I wrote a
verilog-2005 parser using antlr/java about a year ago (never
released it). Now I'm into ruby and writing a general parser
that has a superset of the features in antlr. Here is my first
cut at it:
Now that my cursor package (using this for both my character
and token streams) is to a good point, I'm back to working on
my grammar package (renamed because of another rubyforge
"syntax" project).
I see a file that is downloadable (syntax.rb) on the RAA link, but
there are no downloadable files at the grammar page on RubyForge. Will
you be releasing an update soon?
I wouldn't mind making a verilog parser the first target of
this.
How close is it to EBNF? I'm interested in doing a VHDL parser - how much
tweaking would I need to do to the VHDL EBNF to get something working?
After we've got Verilog and VHDL parsers working would anyone be
interested in a RubySynthesis package? Maybe verification? Or perhaps
more realistically just translation between VHDL <-> Verilog? An
automatic testbench generator would be nice (and certainly doable) as
well.
Phil
···
Eric Mahurin <eric_mahurin@yahoo.com> wrote:
--- Kev Jackson <kevin.jackson@it.fts-vn.com> wrote:
Hi all,
=20
We're about to start a project and we need to be able to
parse RTL=20
files. We want to use ruby, but to save effort we're looking
for a=20
pre-built open-source parser for RTL grammar. If not we'll
have to=20
write our own (no big problem - it'd be an interesting
learning=20
experience at least!).
=20
So first, are there any tools we should be looking at to help
us out? =20
(we're looking at coco-ruby and parsetree at the moment)
Second, if there are no tools currently available and we can
build a=20
Ruby RTL parser would anyone be interested in us releasing
it? (I only=20
work here, I'm not sure if the company would allow us to, but
if it's=20
possible would people be interested?)
=20
Kev
=20
=20
=09
____________________________________________________
Start your day with Yahoo! - make it your home page=20 http://www.yahoo.com/r/hs=20
=20
I'm wondering, what did you use this for? I've been looking for free
(open source preferably) synthesis tools for my FPGA collection, and
have found nothing. I figured it was because "compiling" verilog to
netlists for use on an FPGA is really hard, and the FPGAs themselves
are not well documented internally. What do you do with a Verilog or
VHDL parser, if you can't actually implement your designs?
···
On 01/08/05, Eric Mahurin <eric_mahurin@yahoo.com> wrote:
I'd be interested. I'm in the IC design industry. I wrote a
verilog-2005 parser using antlr/java about a year ago (never
released it).
In article <84fb38e305080207325f7a0fb@mail.gmail.com>,
I'd be interested. I'm in the IC design industry. I wrote a
verilog-2005 parser using antlr/java about a year ago (never
released it).
I'm wondering, what did you use this for? I've been looking for free
(open source preferably) synthesis tools for my FPGA collection, and
have found nothing. I figured it was because "compiling" verilog to
netlists for use on an FPGA is really hard, and the FPGAs themselves
are not well documented internally.
Certainly and this is by design. Xilinx and Altera are very secretive,
they don't want people reverse engineering their FPGAs. Not that it would
be a huge problem because they're well protected by patents.
That said, I believe you can use Icarus (open source Verilog
simulator and now synthesis tool) to synthesize to some of the older
Xilinx architectures. Also, it can't be impossible to get the needed
information (Synplicity, for example, makes FPGA synthesis tools that
target Xilinx, Altera and others' parts), but there may be NDA forms to
sign. I suspect the bitstream files are the tricky part.
What do you do with a Verilog or
VHDL parser, if you can't actually implement your designs?
Actually there are lots of possibilities if you have Verilog/VHDL parsers:
1) You could create translators between the two or to cycle-based
C or SystemC.
2) You could create a testbench generation tool. The tool would look at
your toplevel entity/module and then it could create the skeleton for your
testbench. Of course, you don't need a full parser for this, but if you
have one it'll make things easier.
3) It would be possible to create verification and code analysis tools.
4) Synthesis/Tech mapping. Nothing would stop you from creating
VHDL/Verilog or EDIF netlists (gate level). Because Ruby is a very
flexible language it would be interesting to use it to develop an
experimental synthesis platform where you could easily try new algorithms,
datastructures, etc.
....lots of possibilities.
Phil
···
tsuraan <tsuraan@gmail.com> wrote:
On 01/08/05, Eric Mahurin <eric_mahurin@yahoo.com> wrote:
That said, I believe you can use Icarus (open source Verilog
simulator and now synthesis tool) to synthesize to some of the older
Xilinx architectures. Also, it can't be impossible to get the needed
information (Synplicity, for example, makes FPGA synthesis tools that
target Xilinx, Altera and others' parts), but there may be NDA forms to
sign. I suspect the bitstream files are the tricky part.
That's cool to know. I'll have a look that those projects.
Actually there are lots of possibilities if you have Verilog/VHDL parsers:
1) You could create translators between the two or to cycle-based
C or SystemC.
2) You could create a testbench generation tool. The tool would look at
your toplevel entity/module and then it could create the skeleton for your
testbench. Of course, you don't need a full parser for this, but if you
have one it'll make things easier.
3) It would be possible to create verification and code analysis tools.
4) Synthesis/Tech mapping. Nothing would stop you from creating
VHDL/Verilog or EDIF netlists (gate level). Because Ruby is a very
flexible language it would be interesting to use it to develop an
experimental synthesis platform where you could easily try new algorithms,
datastructures, etc.
....lots of possibilities.
Ok, that's cool. I was sort of hoping you'd point me towards the
elusive OpenXilinxTools, the mythical totally free implementation of
the Xilinx software, but I guess I'll have to keep looking
